Synopsys Resumes ‘SNUG Taiwan 2023 User Conference’ – Introducing AI-powered EDA tool,

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Unveiling the AI-enhanced EDA design tool

After a three-year-long pandemic hiatus, Synopsys, a leading company in electronic design automation (EDA), has finally resumed on-the-ground activities in 2023. The ‘SNUG Taiwan 2023 User Conference’ recently witnessed a keynote speech from Aart de Geus, Synopsys’s CEO, who flew from the United States to Taiwan. The talk detailed the evolution of EDA technology and its progression in IC design processes. He also outlined how to introduce EDA design tools assisted by AI into the design process, announcing the new solution for improving design efficiency and productivity. Nearly a thousand industry experts attended the event, marking a triumphant return.

Synopsys Users Group (SNUG) – Over 20 Years of History in Taiwan

SNUG, one of the largest technical conferences in Taiwan, mainly serves the semiconductor design and manufacturing industry and has been hosted in Taiwan for over 20 years. This year’s event saw over 20 leading semiconductor manufacturers share knowledge on design research and introduce advancements in over 40 IC design technologies. Through this conference, Synopsys announced its latest AI application solutions.

New Perspectives Brought by AI – Reducing Design Schedules and Human Costs with

Aart de Geus emphasized that the ‘Design Space Optimization AI’ (, first announced by Synopsys three years ago, is the inaugural self-learning AI application targeting chip design optimization. He revealed that this solution has already been adopted in over 200 commercial design projects with successful chip optimization and tape-outs, establishing AI as a crucial technology in chip design.

The newly announced is the first AI-driven solution as an EDA development tool that covers the entire EDA process, including design, verification, testing, and manufacturing. As a result, engineers can optimize all design processes using deep learning and AI, flexibly scaling and managing more workloads on individual machines or in cloud environments.

Tackling IC Design Challenges with

One of the most time-consuming steps in chip design is achieving the verification coverage goal and performing convergence and regression analysis. This requires understanding comprehensive test coverage. can accelerate the transition of designs using automated processes and generate test cases. It reduces the need to manually generate tests and increases the precision of predictive error detection and coverage range.

Additionally, the automatic test generation feature can decrease silicon defect coverage, optimize test patterns, and expedite results. Using AI allows for more precise and efficient detection of chip design defects and errors, surpassing traditional technologies. Machine learning can identify potential fault patterns and indicators during chip design through training, enabling chip designers to detect and diagnose faults more quickly and accurately, reducing the number of errors or defects during the verification process.

The Future and Evolution of

Synopsys aims to use AI to solve complex problems in chip design, improving engineering efficiency and productivity. Moving forward, Synopsys intends to further develop to provide better, faster, and more cost-effective solutions to propel the semiconductor industry.

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